Title:
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3904497
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain a processed result equal to or better than in the case loading a maximum number of wafers under the same processing conditions.
SOLUTION: In a film forming process by a vertical batch hot wall low pressure CVD system in an IC manufacturing method, wafers W are loaded to a support groove 15 of a boat 11 with an interval of one stage and the total loading number of wafers is 86. That is, the interval of the wafers W is selected to be 10.4 mm that is twice the interval of 5.2 mm when the maximum loadable number to the boat 11 is 172. That is, the fill dummy wafers to make the processing conditions the same are omitted. However, side dummy wafers are located to upper and lower parts of a wafer group. Even when the processing condition of film forming is selected the same as the film forming processing condition at the maximum loading number of wafers, the film thickness uniformity in the wafer face as to a product wafer group can be controlled within a permissible range. The cost can be reduced through the omission of the fill dummy wafers.
Inventors:
Takeo Hanashima
Hironobu Miya
Soyuki Nakao
Tadao Mitsuda
Hironobu Miya
Soyuki Nakao
Tadao Mitsuda
Application Number:
JP2002267031A
Publication Date:
April 11, 2007
Filing Date:
September 12, 2002
Export Citation:
Assignee:
Hitachi Kokusai Electric Co., Ltd.
International Classes:
H01L21/205; H01L21/22; H01L21/324; (IPC1-7): H01L21/205; H01L21/22; H01L21/324
Domestic Patent References:
| JP2003051497A |
Attorney, Agent or Firm:
Kajiwara Tatsuya
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