Title:
MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3906005
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device using a dummy gate for shortening RPT greatly and improving the processing accuracy in gate dimensions.
SOLUTION: The manufacturing method for a semiconductor device includes a step for forming a gate on a semiconductor substrate, a step for implanting impurity in the semiconductor substrate with a mask of the dummy gate and forming a source/drain diffusion region, a step for forming an insulating film around the dummy gate, a step for removing the dummy gate and forming an opening part, and a step for forming a gate electrode at the opening part through a gate insulating film. The method forming the dummy gate includes a step for applying polymer made of excessive carbon composition and forming a polymer film, a step for forming a photo-resist pattern on the polymer film, and a step for transcribing the photo-resist pattern onto the polymer film.
Inventors:
Kyoichi Suguro
Koji Matsuo
Atsushi Murakoshi
Yasuhiko Sato
Hiromi Niiyama
Koji Matsuo
Atsushi Murakoshi
Yasuhiko Sato
Hiromi Niiyama
Application Number:
JP2000087651A
Publication Date:
April 18, 2007
Filing Date:
March 27, 2000
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G03F7/40; H01L29/78; H01L21/027; H01L21/265; H01L21/266; H01L21/28; H01L21/336; H01L21/8238; H01L21/8242; H01L27/092; H01L27/108; H01L29/423; H01L29/43; H01L29/49; (IPC1-7): H01L29/78; G03F7/40; H01L21/265; H01L21/027; H01L21/8238; H01L27/092; H01L27/108; H01L21/8242; H01L29/43; H01L21/336
Domestic Patent References:
| JP4023425A | ||||
| JP6168918A | ||||
| JP53101265A |
Attorney, Agent or Firm:
Takehiko Suzue
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai