Title:
半導体装置の作製方法
Document Type and Number:
Japanese Patent JP4204649
Kind Code:
B2
Abstract:
A process for fabricating a semiconductor device having a multilayer wiring, comprising steps of: forming a first wiring or electrode on a substrate; forming an insulating film which covers the first wiring or electrode; forming a contact hole to the first wiring or electrode through the insulating film; forming a wiring for contacting the first wiring or electrode inside the contact hole; and removing the protruded portion of the contact wiring and flattening the insulating film at the same time in an electrolytic solution by means of chemical mechanical polishing using the contact wiring as the anode. Also claimed is an apparatus for polishing the surface of a semiconductor device during its fabricating the device, comprising: means for performing chemicomechanical polishing; and means for supplying electric current to the electrode of the semiconductor device.
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Inventors:
Shunpei Yamazaki
Satoshi Teramoto
Satoshi Teramoto
Application Number:
JP4214996A
Publication Date:
January 07, 2009
Filing Date:
February 05, 1996
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/768; H01L23/52; B23H5/08; H01L21/306; H01L21/3063; H01L21/3105; H01L21/3205; H01L21/321; H01L21/336; H01L29/786
Domestic Patent References:
| JP7130848A | ||||
| JP8074100A |