Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP7042726
Kind Code:
B2
Abstract:
In a memory cell forming region including a dummy cell region, a plurality of fins which are parts of a semiconductor substrate, protrude from an upper surface of an element isolation portion and are formed adjacent to each other. A distance between a fin closest to a dummy fin among the plurality of fins and the dummy fin is shorter than a distance between two fins adjacent to each other. As a result, a position of an upper surface of the element isolation portion formed between two fins adjacent to each other and a position of an upper surface of the element isolation portion STI formed between the fin closest to the dummy fin and the dummy fin is lower than a position of an upper surface of the element isolation portion STI formed in a shunt region.
Inventors:
Uchimura Katsuhiro
Application Number:
JP2018189130A
Publication Date:
March 28, 2022
Filing Date:
October 04, 2018
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L27/11575; H01L21/336; H01L21/76; H01L21/8234; H01L27/088; H01L27/11565; H01L27/11568; H01L29/788; H01L29/792
Domestic Patent References:
| JP2013038213A | ||||
| JP2018056453A | ||||
| JP2008311503A |
Attorney, Agent or Firm:
Tsutsui International Patent Office