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Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP4239015
Kind Code:
B2
Abstract:
The task of the present invention is to enable formation of a gate insulating film structure having a good-quality interface between a silicon oxide film and silicon in an interface between a high dielectric constant thin film and a silicon substrate to provide a semiconductor device and a semiconductor manufacturing method which are capable of improving interface electrical characteristics, which has been a longstanding task in practical use of a high dielectric constant insulating film. A metal layer deposition process and a heat treatment process which supply metal elements constituting a high dielectric constant film on a surface of a base silicon oxide film 103 allow the metal elements to be diffused into the base silicon oxide film 103 to thereby form an insulating film structure 105 as a gate insulating film, after forming the base silicon oxide film 103 on a surface of a silicon substrate 101. The insulating film structure 105 including a silicate region comprises a silicon oxide film region, a silicate region, and a metal rich region, forming a silicate structure having composition modulation in which composition of metal increases as closer to an upper portion, and the composition of silicon increases as closer to a lower portion.

Inventors:
Heiji Watanabe
Hirohito Watanabe
Toru Tatsumi
Fujieda Shinji
Application Number:
JP2004521225A
Publication Date:
March 18, 2009
Filing Date:
July 16, 2003
Export Citation:
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Assignee:
NEC
International Classes:
H01L29/78; H01L21/28; H01L21/316; H01L29/51
Domestic Patent References:
JP2001332547A
JP2002184773A
JP2001257344A
JP62118559A
JP2003158262A
JP2003008011A
JP2003204061A
JP58093331A
Other References:
渡部平司,ZrO2/SiO2/Si界面制御とゲート絶縁膜への応用,半導体・集積回路技術 第62回シンポジウム講演論文集,2002年 6月 6日,pp.13-18
渡部平司,組成変調Zrシリケート薄膜の構造解析と電気特性評価,第49回応用物理学関係連合講演会講演予稿集 第2分冊,2002年 3月27日,p.830
Attorney, Agent or Firm:
Haruo Hamada