Document Type and Number:
Japanese Patent JP4264750
Kind Code:
B2
Abstract:
To provide a semiconductor chip comprising two chips, having planar symmetric terminal arrays of common structure, a semiconductor device and their manufacturing method, a circuit board and an electronic apparatus thereof.
The position of a first terminal T1of a first semiconductor chip 100 is plane symmetric, with respect to the position of the second terminal T2of a second semiconductor chip 200. First buffer circuits C1, C2of the first semiconductor chip 100 are identical, at least in design, to the second buffer circuits C1, C2of the second semiconductor chip 200. First and second internal circuits (a decoder 11, a control circuit 21, and the like) are identical, at least in design. Interconnections 55, 61 are formed into different patterns.
COPYRIGHT: (C)2006,JPO&NCIPI
Inventors:
Kodaira Satoru
Takahiro Kumagai
Yasuhiko Tomohiro
Application Number:
JP2005165096A
Publication Date:
May 20, 2009
Filing Date:
June 06, 2005
Assignee:
Seiko Epson Corporation
International Classes:
G11C11/41; H01L21/822; G11C11/401; H01L25/00; H01L27/04
Domestic Patent References:
| JP4133464A | | | | |
| JP7130949A | | | | |
| JP3228352A | | | | |
| JP5251495A | | | | |
| JP9017979A | | | | |
| JP7297354A | | | | |
| JP3169048A | | | | |
Attorney, Agent or Firm:
Yukio Fuse
Mitsue Obuchi
Takekoshi Noboru
