Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP4377721
Kind Code:
B2
Abstract:
Disclosed is a semiconductor device of n-type MOSFET structure, which comprises a semiconductor substrate having a device isolation region, diffusion regions formed in the semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a F-containing NiSi layer formed on the diffusion regions and containing F atoms at a concentration of 3.0×1013 cm−2 or more in areal density, wherein a depth from the junction position formed between the diffusion region and the semiconductor substrate to the bottom of the F-containing NiSi layer is confined within the range of 20 to 100 nm, and the concentration of F atoms at an interface between the F-containing NiSi layer and the semiconductor substrate is 8.0×1018 cm−3 or more.
Inventors:
Masakatsu Domei
Application Number:
JP2004068915A
Publication Date:
December 02, 2009
Filing Date:
March 11, 2004
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/28; H01L29/78; H01L21/3205; H01L21/324; H01L21/336; H01L21/4763; H01L21/477; H01L21/8238; H01L21/8242; H01L27/08; H01L27/092; H01L27/108; H01L29/417; H01L29/786
Domestic Patent References:
| JP10178171A | ||||
| JP2002141504A | ||||
| JP7066146A | ||||
| JP2002543623A | ||||
| JP10083990A | ||||
| JP10242081A | ||||
| JP8301612A |
Attorney, Agent or Firm:
Takehiko Suzue
Kurata Masatoshi
Satoshi Kono
Makoto Nakamura
Sadao Muramatsu
Kurata Masatoshi
Satoshi Kono
Makoto Nakamura
Sadao Muramatsu