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Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP4769837
Kind Code:
B2
Abstract:

To prevent a short circuit caused by solder reflowing in a semiconductor device.

The semiconductor device comprises a semiconductor chip 2 having a plurality of pads 2c formed on a main plane 2d, a chip component 3 having a connection terminal 3d formed at each end, a module substrate 4 having the semiconductor chip 2 and the chip component 3 mounted thereto, a solder connecting member 5 for connecting the chip component 3 and the substrate side terminal 4a of the module substrate 4 with solder, a gold wire 8 for connecting the pad 2c of the semiconductor chip 2 with the substrate side terminal 4a of the corresponding module substrate 4, and a sealing member covering the semiconductor chip 2, the chip component 3, the solder connection member 5, and the gold wire 8, and comprising a low modulus resin as an insulation silicone resin, a low modulus epoxy resin or the like. The device is prevented from the flowing out of the solder caused by the reflow of the solder at the solder connection member 5.

COPYRIGHT: (C)2009,JPO&INPIT


Inventors:
Masashi Yamaura
Koichi Nakajima
Nobuyoshi Maejima
Mikio Negishi
Tomio Yamada
Tomomi Koizumi
Tsuneo Endo
Application Number:
JP2008089435A
Publication Date:
September 07, 2011
Filing Date:
March 31, 2008
Export Citation:
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Assignee:
Renesas Electronics Corporation
International Classes:
H01L25/00; H01L23/29; H01L23/31
Domestic Patent References:
JP6061417A
JP11204670A
JP2000156434A
JP11067799A
JP7142762A
JP10126044A
JP2002009200A
Attorney, Agent or Firm:
Yamato Tsutsui