Title:
半導体装置の製造方法および半導体装置
Document Type and Number:
Japanese Patent JP5023072
Kind Code:
B2
Abstract:
A plug (43) as a lower electrode is embedded in the opening (42) of an insulating film (41) formed on a semiconductor substrate, and a phase change memory is formed by forming a recording layer (52) composed of chalcogenide and an upper electrode film (53) on the insulating film (41) embedding the plug (43). An amorphous region (52a) of high resistance is formed near the interface of an insulating film (51) and the recording layer (52) immediately after ending a wafer process, and the resistance is decreased by initializing the recording layer (52). When initializing the recording layer (52), a current is fed to the recording layer (52) by applying a voltage between the plug (43) and the upper electrode film (53) while heating the semiconductor substrate. A portion of the amorphous region (52a) located above the plug (43) is thereby crystallized and the resistance of the recording layer (52) is decreased between the plug (43) and the upper electrode film (53).
Inventors:
Takahiro Morikawa
Motoyasu Terao
Norikatsu Takaura
Kenzo Kurochi
Motoyasu Terao
Norikatsu Takaura
Kenzo Kurochi
Application Number:
JP2008548103A
Publication Date:
September 12, 2012
Filing Date:
November 30, 2006
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L27/105; H01L27/10; H01L45/00
Domestic Patent References:
| JP2004289029A | 2004-10-14 | |||
| JP2006108670A | 2006-04-20 | |||
| JP2006156886A | 2006-06-15 | |||
| JP2005260014A | 2005-09-22 |
Attorney, Agent or Firm:
Yamato Tsutsui