Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP5259380
Kind Code:
B2
Abstract:
A semiconductor-device manufacturing method includes steps of performing a sidewall fabrication thereby forming a first pattern structure; measuring an amount of displacement of line portions of the first pattern structure; correcting an overlay specification for an overlay of the first pattern structure and a second pattern structure dynamically based on the amount of displacement; and determining whether an error in the overlay of the first pattern structure and the second pattern structure meets the corrected overlay specification.
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Inventors:
Yuji Kobayashi
Application Number:
JP2008328464A
Publication Date:
August 07, 2013
Filing Date:
December 24, 2008
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/027; G03F7/40; H01L21/3213; H01L21/768
Domestic Patent References:
| JP2008072101A | ||||
| JP2008022004A | ||||
| JP2007027789A | ||||
| JP2004153191A | ||||
| JP2002299202A | ||||
| JP2001272208A | ||||
| JP10064964A | ||||
| JP7326562A | ||||
| JP2005285892A | ||||
| JP2005252025A | ||||
| JP2000133568A |
Foreign References:
| WO2003043064A1 | ||||
| US20050122516 | ||||
| WO2002069047A1 |
Attorney, Agent or Firm:
Hiroaki Sakai