Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP5464853
Kind Code:
B2
Abstract:
To provide a semiconductor device and a method of manufacturing the same capable of suppressing, when a plurality of MIS transistors having different absolute values of threshold voltage is used, the reduction of the drive current of a MIS transistor having a greater absolute value of threshold voltage. The threshold voltage of a second nMIS transistor is greater than the threshold voltage of a first nMIS transistor and the sum of the concentration of lanthanum atom and the concentration of magnesium atom in a second nMIS high-k film included in the second nMIS transistor is lower than the sum of the concentration of lanthanum atom and the concentration of magnesium atom in a first nMIS high-k film included in the first nMIS transistor.
Inventors:
Kazuhiro Onishi
Kazuhiro Tsukamoto
Kazuhiro Tsukamoto
Application Number:
JP2008335656A
Publication Date:
April 09, 2014
Filing Date:
December 29, 2008
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/8234; H01L21/283; H01L21/336; H01L21/8238; H01L21/8244; H01L27/088; H01L27/092; H01L27/11; H01L29/423; H01L29/49; H01L29/78
Domestic Patent References:
| JP2002280461A | ||||
| JP2010056239A | ||||
| JP2008211182A | ||||
| JP2007329237A | ||||
| JP2005025907A | ||||
| JP2010157587A | ||||
| JP2010153752A | ||||
| JP2010123669A |
Attorney, Agent or Firm:
Fukami patent office
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