Title:
半導体集積回路装置の製造方法
Document Type and Number:
Japanese Patent JP5191646
Kind Code:
B2
Abstract:
A technique of manufacturing a semiconductor integrated circuit device is provided for reducing the possibility of attachment of foreign matter to a membrane probe when performing probe inspection using the membrane probe formed by the manufacturing technique. A pressing member for pressing a membrane sheet includes a pressing pin receiving portion relatively disposed above for receiving the tip of a pressing pin of the plunger in a recess, and a membrane sheet pressing portion relatively disposed below. The membrane sheet pressing portion in contact with the membrane sheet has the minimum plane size to enable pressing of the entire surface of one chip of interest to be subjected to the probe inspection.
Inventors:
Akio Hasebe
Yasuhiro Motoyama
Naritsuka Yasunori
Seigo Nakamura
Yasuhiro Motoyama
Naritsuka Yasunori
Seigo Nakamura
Application Number:
JP2006288642A
Publication Date:
May 08, 2013
Filing Date:
October 24, 2006
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G01R1/073; H01L21/66
Domestic Patent References:
| JP2005024377A | ||||
| JP8220138A | ||||
| JP3104864U |
Attorney, Agent or Firm:
Yamato Tsutsui