Title:
半導体記憶装置の製造方法
Document Type and Number:
Japanese Patent JP3584155
Kind Code:
B2
Abstract:
A selective transistor is formed on a silicon substrate (1). A lower electrode (5) comprising Ti film and Pt film, a SrBi2Ta2O9 film, an upper electrode (7) comprising Pt film, and a TiO2 film (9) having such a configuration as to cover the upper electrode (7) and the SrBi2Ta2O9 film (6) are formed on an interlayer insulating film (4) formed on the silicon substrate including the selective transistor. The upper electrode (7) and a drain region (12b) of the selective transistor are electrically connected to each other by metal wiring (11) via contact holes formed on the upper electrode (7) and the drain of the selective transistor. According to the semiconductor storage device having the above construction, the TiO2 film and the lower electrode can be patterned continuously in one process. Therefore, the number of processes involved can be reduced and a cost reduction can be achieved.
Inventors:
Kinoshita Tagao
Application Number:
JP1629098A
Publication Date:
November 04, 2004
Filing Date:
January 29, 1998
Export Citation:
Assignee:
Sharp Corporation
International Classes:
H01L21/8247; H01L21/8242; H01L21/8246; H01L27/10; H01L27/105; H01L27/108; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L27/105
Domestic Patent References:
| JP7111318A | ||||
| JP8335673A | ||||
| JP11017124A | ||||
| JP11135736A | ||||
| JP11121704A | ||||
| JP10223852A | ||||
| JP7273297A | ||||
| JP7078890A |
Attorney, Agent or Firm:
Hiroshi Yamazaki
Atsushi Maeda
Yukinori Nakakura
Atsushi Maeda
Yukinori Nakakura