Title:
半導体記憶装置及の製造方法
Document Type and Number:
Japanese Patent JP5471134
Kind Code:
B2
Abstract:
Disclosed herein is a semiconductor memory device, including: a first electrode formed on a substrate; an ion source layer formed on an upper layer of the first electrode; and a second electrode formed on an upper layer of the ion source layer. Resistance change type memory cells in each of which either a surface of the first electrode or a surface of the ion source layer is oxidized to form a resistance change type memory layer in an interface between the first electrode and the ion source interface are arranged in a array.
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Inventors:
Emiko Tagawa
Tetsuya Mizuguchi
Ichiro Fujiwara
Akira Kawauchiyama
Satoshi Sasaki
Naomi Yamada
Tetsuya Mizuguchi
Ichiro Fujiwara
Akira Kawauchiyama
Satoshi Sasaki
Naomi Yamada
Application Number:
JP2009182036A
Publication Date:
April 16, 2014
Filing Date:
August 05, 2009
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H01L27/10; H01L45/00; H01L49/00
Domestic Patent References:
| JP2007189087A | ||||
| JP2006173267A | ||||
| JP2009129992A | ||||
| JP2009043758A |
Foreign References:
| WO2008068800A1 |
Attorney, Agent or Firm:
Takahisa Sato