MANUFACTURING METHOD OF WIRING BOARD

Japanese Patent JP2016105512

A

PROBLEM TO BE SOLVED: To provide a manufacturing method of a wiring board that has excellent connection reliability between a semiconductor element connection pad and an electrode of a semiconductor element by suppressing the occurrence of void between the semiconductor element connection pad and a nickel plating layer, and has a lead connection pad and a lead terminal firmly connected to each other.SOLUTION: A manufacturing method of a wiring board including the steps of: forming, on the top face of a first insulating layer 1, a semiconductor element connection pad 3 having an arithmetic average roughness Ra of an exposed surface from 150 to 1000 nm; forming a second insulating layer 2 thereon; forming a lead connection pad 4 having an arithmetic average roughness Ra of an exposed surface from 100 to 200 μm on the surface of the second insulating layer 2; forming, in the second insulating layer 2, openings 5 to expose the semiconductor element connection pad 3 by laser processing and levelling the semiconductor element connection pad 3 to be exposed to have an arithmetic average roughness Ra in a range from 20 to 80 nm; and depositing a nickel plating layer 7 on the surface of the semiconductor element connection pad 3 and the surface of the lead connection pad 4.SELECTED DRAWING: Figure 2

HOSOI YOSHIHIRO
TAGUCHI TAKAYUKI
YUGAWA HIDETOSHI

JP2016039307A

June 09, 2016

March 01, 2016

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KYOCERA CIRCUIT SOLUTIONS INC

H05K3/34; H05K3/24; H05K3/26

JP2000332408A	2000-11-30
JP2011155251A	2011-08-11
JP2007318098A	2007-12-06
JP2009105393A	2009-05-14
JPH07202368A	1995-08-04
JPWO2008143099A1	2010-08-05

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