MASK PATTERN CORRECTING METHOD AND ITS CORRECTING SYSTEM

Title:

MASK PATTERN CORRECTING METHOD AND ITS CORRECTING SYSTEM

Document Type and Number:

Japanese Patent JP3895851

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To correct a proximity effect resulting from a process, caused by a difference in etching conversion, and produced when a plurality of gate materials are etched in one and the same device.
SOLUTION: After a correction region is extracted (step S1), an n+-type polycrystalline Si gate layer is extracted (step S2). Distance between adjoining patterns in the n+-type polycrystalline Si gate layer is calculated so as to include a p+-type polycrystalline Si gate layer (step S3), and the patterns in the n+-type polycrystalline Si gate layer are corrected (step S5) by referring to a correction table for the adjoining patterns in the n+-type polycrystalline Si gate layer (step 4). Then, the p+-type polycrystalline Si gate layer is extracted (step S6) and distance between adjoining patterns in the p+-type polycrystalline Si gate layer is calculated so as to include the n+-type polycrystalline Si gate layer (step S7). The patterns in the p+-type polycrystalline Si gate layer are corrected (step S9) by referring to a correction table for the adjoining patterns in the p+-type polycrystalline Si gate layer (step 8).

Inventors:

Koji Hashimoto
Aoyama Hisako
Soichi Inoue
Kazuko Yamamoto
Sachiko Kobayashi

Application Number:

JP33876297A

Publication Date:

March 22, 2007

Filing Date:

December 09, 1997

Export Citation:

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Assignee:

Toshiba Corporation

International Classes:

G03F1/36; G03F1/72; G03F7/20; H01L21/027; (IPC1-7): G03F1/08; H01L21/027

Domestic Patent References:

JP8321450A
JP5267251A
JP7235673A

Attorney, Agent or Firm:

Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Sadao Muramatsu
Ryo Hashimoto

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