To provide a matched filter with a small size and less power consumption by miniaturizing the circuit of the matched filter without deteriorating synchronization detection accuracy.

The matched filter is provided with correlation detection circuits 60-615 whose number is equal to 1/4 of a spread code length. A multiplier 71 of each of the correlation detection circuits 60-615 multiplies data received synchronously with a chip rate with a spread code of a 1/4 code length that a spread code register 50 generates while shifting it synchronously with the chip rate, and an adder 72 sequentially sums the products. A register 73 of the correlation detection circuits 60-615 respectively stores the sums summed in each of the adders 72, 72, etc., over one spread code period generated and designated by an enable signal generated from an enable signal generating section 51, an output selector 52 sequentially reads the final sum stored in each register 73 and outputs the final sum as correlation detection data.