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Title:
MATCHING CIRCUIT FOR FIELD EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPH01245703
Kind Code:
A
Abstract:

PURPOSE: To prevent the deterioration in the RF characteristic by providing an input side dielectric base having a 1st strip line connecting to a 1st external circuit and an output side dielectric base having a 2nd strip line connecting to a 2nd external circuit so as to eliminate a phase difference in RF signals passing through a FET of a multi-cell structure.

CONSTITUTION: A gate electrode 4, an input side strip line 2, a drain electrode 5 and an output side strip line 7 are connected by a metallic line 8. The input side strip line 2 is connected to the input side matching circuit at a point A being at one side of the multi-cell FET 3. The strip line is connected at points A, B located at the cell at the end of the FET to the input/output matching circuit to allow the RF signal passing from the point A to the point B to have no phase difference because the distance is the same even if the RF signal passes any cell of the multi-cell FET. Thus, the deterioration in the RF characteristic due to the phase difference is eliminated.


Inventors:
WASA KENJI
Application Number:
JP7406288A
Publication Date:
September 29, 1989
Filing Date:
March 28, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L29/812; H01L21/338; H01L23/12; H01L29/80; H01P5/08; H03F3/60; (IPC1-7): H01L23/12; H01L29/80; H01P5/08; H03F3/60
Domestic Patent References:
JPS61140211A1986-06-27
Attorney, Agent or Firm:
Yutaro Kumagai