Title:
MATCHING FOR DIGITAL PATTERN USING ANALOG LOGIC
Document Type and Number:
Japanese Patent JP3391973
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To solve a problem such as the complication of a circuit or the increase of a delay time due to the increase of the number of matching.
SOLUTION: Quick, low power, and small-scaled approach for the matching of a digital pattern provides the comparison of an input pattern 218 with a reference pattern 219 by each bit for judging coincidence. In an execution example, incoincidence turns each current source 207-209 into a connected state. When currents from the incoincidence are beyond the maximum value (Imax) of a current sink, a pattern incoincidence output 213 is increased. The reference pattern and the number of bits which must be coincident can be easily programmed. This approach is especially effective in 'fuzzy' matching in which N bits among an M bit pattern must be coincident for recognizing that the patterns are coincident.
Inventors:
Glen Edward Offord
Jeff Ray Lee Sontag
Jeff Ray Lee Sontag
Application Number:
JP4448396A
Publication Date:
March 31, 2003
Filing Date:
March 01, 1996
Export Citation:
Assignee:
AT&T CORP.
International Classes:
G06G7/14; G06F7/02; H03K19/20; (IPC1-7): G06G7/14; H03K19/20
Domestic Patent References:
| JP9500749A |
Attorney, Agent or Firm:
Masao Okabe (2 outside)