PURPOSE: To attain the high speed of a matrix arithmetic operation regardless of the size of a matrix by computing the arithmetic result of a specific matrix in a specific clock cycle time.

CONSTITUTION: Input data X are four clock-shifted by a shift register 1001, and inputted to a multiplier 104. On the other hand, K4n inputted to the other input of the multiplier 104 are successively K41, K42, K43, and K44 when t=t4. Those data are computed by the multiplier 104, adder 105, latch 702, and feedback circuit 701, and Y41 are outputted to S4n when t=t8. In the same way, the arithmetic result is obtained at S3n, S2n, and S1n. Input X3, X2, and X1 to each multiplier are inputted earlier in each one clock, so that the obtained result can be inputted earlier in each one clock. They are successively selected by a selector 1003, latched by a latch 110 by a clock CK, and Y is outputted.