Title:
MATRIX ARRAY SUBSTRATE
Document Type and Number:
Japanese Patent JP2587754
Kind Code:
B2
Abstract:
PURPOSE: To make the title matrix array increasing the electrostatic breakdown strength by a method wherein resistors are inserted into the parts outside the matrix array region on a signal input side per one multiple respective lines of multiple gate lines or source lines.
CONSTITUTION: The aluminum wiring 13 connected to source 9-1 of transistor 2 is extended in the vertical direction to be source line 3 while the other aluminum wiring 13 connected to drain 9-2 of the transisto 2 is connected to a capacitor 6 and a liquid crystal cell 7. On the other hand, MOS type transistors 2 are arranged in matrix source line 3 outside the matrix region of gate line 4 while the other resistors 14 are connected to the outside of the gate lines 4. Accordingly, the resistors 14, 15 can be inserted into the parts outside the matrix array region on a signal input side of gate lines 4 or source lines 3 thereby enabling the electrostatic breakdown strength to be notably increased for manufacturing a highly reliable liquid crystal display.
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Inventors:
KODAIRA TOSHIMOTO
OOSHIMA HIROYUKI
MANO TOSHIHIKO
OOSHIMA HIROYUKI
MANO TOSHIHIKO
Application Number:
JP17034192A
Publication Date:
March 05, 1997
Filing Date:
June 29, 1992
Export Citation:
Assignee:
SEIKO EPSON CORP
International Classes:
G02F1/1345; G02F1/136; G02F1/1368; H01L21/822; H01L27/04; H01L27/10; H01L27/12; H01L29/78; H01L29/786; (IPC1-7): H01L29/786; G02F1/1345; G02F1/136; H01L21/822; H01L27/04; H01L27/10; H01L27/12
Domestic Patent References:
| JP354475B2 |
Attorney, Agent or Firm:
Kisaburo Suzuki (1 outside)