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Title:
MATRIX DISPLAY DEVICE
Document Type and Number:
Japanese Patent JPS63173021
Kind Code:
A
Abstract:

PURPOSE: To obtain a high display grade at a low cost by laminating 1st conductor layers having spacings, 1st resin layers, semiconductor layers consisting of a compd. of arsenic As, sulfur S and selenium Se, 2nd resin layers and further 2nd conductor layers successively on a substrate.

CONSTITUTION: A display medium is sandwiched between a nonlinear two- terminal element array having the composite layers consisting of the 1st conductor layers 2 which have the spacings, the 2nd conductor layers 6 which are provided in plural pieces each with each of the conductor layers 2, the 1st resin layers 3 which are interposed between the 1st conductor layers 2 and the 2nd conductor layers 6 and are electrically cascade-connected, the semiconductor layers which consist of the compd. of the arsenic As, sulfur S and selenium Se and the 2nd resin layers 5 successively on the substrate 1 and the 2nd substrate having band-shaped electrodes. A nonlinear current-voltage characteristic is, therefore, realized and the improvement in contrast characteristic is permitted. Since the specific dielectric constant of the compd. of the arsenic As, sulfur S and selenium Se forming the semiconductor layers 4 is as small as ≤10, the formation of the nonlinear element to a relatively large shape is possible and the improvement in the yield is expected.


Inventors:
KIKUCHI ISAKO
FUJITA SHINGO
YAMAZOE HIROSHI
Application Number:
JP535087A
Publication Date:
July 16, 1988
Filing Date:
January 13, 1987
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L49/02; G02F1/133; G02F1/163; G02F1/167; G02F1/17; G02F1/19; (IPC1-7): G02F1/133; G02F1/17; G02F1/19; H01L49/02
Attorney, Agent or Firm:
Toshio Nakao



 
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