Title:
マトリクスディスプレイ
Document Type and Number:
Japanese Patent JP2005512113
Kind Code:
A
Abstract:
A matrix display has pixels 2 each including a programmable memory element 30 arranged in parallel across capacitance 28. The voltage on the capacitance controls a display element 25. The arrangement can be run in a normal mode, with all of the memory elements 30 in a high resistance state so that the matrix display can be driven dynamically. Alternatively, in a static (low power) mode of operation, the memory elements 30 are programmed with a static image which may be displayed without driving the data lines 6.
Inventors:
Shannon, John M
Application Number:
JP2003529438A
Publication Date:
April 28, 2005
Filing Date:
September 16, 2002
Export Citation:
Assignee:
Koninklijke Philips Electronics N.V.
International Classes:
G09G3/20; G09G3/30; G09G3/32; G09G3/36; G11C13/00; H01L51/50; G02F1/133; (IPC1-7): G09G3/30; G02F1/133; G09G3/20; G09G3/36; G11C13/00; H05B33/14
Attorney, Agent or Firm:
Tadahiko Ito
Shinsuke Onuki
Tadashige Ito
Shinsuke Onuki
Tadashige Ito