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Title:
MEANS FOR DISPLAY SIGNAL PROCESSING AND MEMORY CONTROL METHOD FOR THE SIGNAL PROCESSING MEANS
Document Type and Number:
Japanese Patent JP3967414
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To reduce a power consumption by integrating a video signal processing and a memory block in PDP signal processing into one chip, and making an interface between the memory and the logic execute in a LSI.
SOLUTION: It can be done easily to divide inputted 8-bit R, G, B data to each line unit divided in bit unit; store them once in a memory bank 40; and divide the data written in the memory bank to picture elements corresponding to address driver while reading them in bit unit. Therefore, since it is possible to integrate input terminals 10R, 10G, 10B up to output terminals 70-1 to 70-8 into one chip, it becomes possible to eliminate interfaces between logic and memory such as a memory selection means and a memory, and between memory and a second video signal processing means, etc., which have been configured from separate chips up to now, and consequently, it is possible to reduce a power consumption in an input buffer and an output buffer of the interfaces.


Inventors:
Kentaro Teranishi
Yuichiro Kimura
Akihiro
Hajime Kimura
Yasutaka Tsuru
Application Number:
JP4535797A
Publication Date:
August 29, 2007
Filing Date:
February 28, 1997
Export Citation:
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Assignee:
株式会社日立製作所
International Classes:
G09G3/296; (IPC1-7): G09G3/28
Domestic Patent References:
JP5041841A
JP7140922A
JP6180558A
JP7168159A
Attorney, Agent or Firm:
Patent Business Corporation Daiichi International Patent Office
Yoshiaki Numagata
Takio Sumiyoshi