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Title:
MEASURING METHOD FOR RESISTIVITY OF SILICON EPITAXIAL WAFER GROWTH LAYER
Document Type and Number:
Japanese Patent JPH04127553
Kind Code:
A
Abstract:

PURPOSE: To enable the resistivity of a growth layer to be measured even if it is 1μm or below in thickness by a method wherein a variable bias voltage is applied between a conductive layer and the back of a silicon epitaxial wafer, the chopped light is made to impinge on the growth layer, and a surface photovoltage induced on the surface of the growth layer is measured.

CONSTITUTION: A junction wafer directly joined to a silicon single crystal mirror surface wafer grown in a CZ method is polished through a normal mirror surface technique so as to evaluate the effectiveness of a resistivity evaluation technique of a semiconductor thin layer through a Schottky CV method and a four-point method. A silicon single crystal thin film layer is controlled to be as thick as 1μm or so, and a resistivity evaluation technique is applied to a part of the film layer whose thickness is smaller or larger than 1μm. A resistivity previously obtained through a four-point method on a silicon wafer mirror surface side is used as a true value. A voltage applying insulator organic film is formed through such a method that tin is vapor-deposited on one side of a polyester film 50μm in thickness. Light rays 560nm in wavelength are used for measurement.


Inventors:
TATE NAOTO
KATAYAMA MASAYASU
Application Number:
JP24911890A
Publication Date:
April 28, 1992
Filing Date:
September 19, 1990
Export Citation:
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Assignee:
SHINETSU HANDOTAI KK
International Classes:
H01L21/66; (IPC1-7): H01L21/66
Domestic Patent References:
JPS57159014A1982-10-01
JPS59171133A1984-09-27
JP64109734A
JPS5982740A1984-05-12
JPH01179339A1989-07-17
Attorney, Agent or Firm:
Shoji Ishihara



 
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