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Title:
MEASURING STRUCTURE FOR EM LIFETIME OF SEMICONDUCTOR INTEGRATED CIRCUIT AND MEASURING METHOD THEREFOR
Document Type and Number:
Japanese Patent JPH11204607
Kind Code:
A
Abstract:

To reduce number of power supplies for applying current and thermostatic chambers in measuring electromigration(EM) lifetime of a semiconductor integrated circuit, by the use of a heated resistance wire as a heat source in turning on a wiring pattern sample, and controlling a junction temperature of the wiring pattern sample.

A heated resistance wire pattern 2 is positioned close to a wiring pattern sample 1. The wiring pattern sample 1 and the resistance wire pattern 2 are electrically insulated to each other via an interlayer film. In turning on the wiring pattern sample 1, the resistance wire pattern 2 is heated and used as a heat source, by applying current to the wiring pattern sample 1 and the resistance wire pattern 2. A junction temperature of the wiring pattern sample 1 is controlled uniformly, by adjusting current applied to the resistance wire pattern 2. Consequently, only one thermostatic chamber is necessary for activation energy measurement, and it is not necessary to prepare thermostatic chambers for each temperature.


Inventors:
ONOZAWA SACHIKO
Application Number:
JP1511498A
Publication Date:
July 30, 1999
Filing Date:
January 08, 1998
Export Citation:
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Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
H01L21/66; H01L21/3205; H01L23/52; (IPC1-7): H01L21/66; H01L21/3205
Attorney, Agent or Firm:
Koji Hagiwara (2 outside)