Title:
MICROCOMPUTER AND ITS TESTING METHOD
Document Type and Number:
Japanese Patent JP3105881
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a microcomputer capable of testing all addresses of a built-in ROM without changing operation modes and its testing method.
SOLUTION: This microcomputer is provided with a read only memory 3 in which a program is stored, an external ROM 2 in which a test program for testing the memory 3 is stored, a central processing unit 7 reading and executing a program or the test program and an instruction outputting circuit which gives an instruction to jump to the address of the ROM 2 to the unit 7 when a ROM test signal is inputted from the outside and also when a reset signal 6 returning the unit 7 to an initial state becomes low. Since a test to the read only memory is executed when a prescribed signal is inputted from the outside to release reset in this way, it is possible to perform a test in an operation mode without having to change operation modes if the operation mode desired to be tested is preliminarily set.
Inventors:
Toshifumi Yanagida
Application Number:
JP4718799A
Publication Date:
November 06, 2000
Filing Date:
February 24, 1999
Export Citation:
Assignee:
NEC IC Microcomputer System Co., Ltd.
International Classes:
G06F11/22; G06F15/78; (IPC1-7): G06F11/22; G06F15/78
Domestic Patent References:
| JP7295850A | ||||
| JP1292443A |
Attorney, Agent or Firm:
Masanori Fujimaki