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Title:
MEMORY ACCESS CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JPH0417043
Kind Code:
A
Abstract:

PURPOSE: To prevent the occurrence of such a case that sending of data from a resource is stopped for a long time due to an arbitration process by starting the arbitration process at the moment when the resource acquires the using right of a bus and sends a bus busy signal to the bus.

CONSTITUTION: A function which sends a signal for controlling memory refreshing operations to a DRAM 8 and another function which makes delivery and reception of signals for reading and writing operations between a resource in a system which makes memory access and the DRAM 8 to which the memory access is made are given to this memory access control circuit 7. A function which monitors a bus busy signal and detects the bus busy signal detecting time from a resource and another function which starts an arbitration process on the basis of the bus busy signal sending time are also given to the circuit 7. Therefore, the arbitration process starting time becomes considerably earlier and the occurrence of such a case that sending of data from a resource is stopped for a long time can be prevented.


Inventors:
OKI MAKOTO
MORI MASAMI
OKABE KAZUYA
KATSUYAMA TAKASHI
Application Number:
JP11971690A
Publication Date:
January 21, 1992
Filing Date:
May 11, 1990
Export Citation:
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Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
G11C11/406; G06F12/00; G06F13/18; (IPC1-7): G06F12/00
Attorney, Agent or Firm:
Toshiaki Suzuki



 
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