PURPOSE: To shorten access time by outputting to DRAM only when higher address value is changed.

CONSTITUTION: After resetting RTS, a counter 12 outputs a UMA/LMA at a strobe AS and the address UA/LA of a circuit 11. The UMA is compared 16 with an output OMA of a former address register 15. As they are discordant at first time, a discordance NE is indicated, and a controlling circuit 17 sends a new address NA to the register 15 and holds the UMA, and at the same time, gives a signal ASE. A multiplexer 13 switches the UMA/LMA and outputs, and receives signals the inverse of RAS, the inverse of CAS, and a DRAM 18 takes in higher and lower addresses and transfers 19 to the circuit 11. At the second time and thereafter, when the UA is unchanged, only the LMA of access of the DRAM appears in a bus 14, and in case the UA is changed, a signal WAI is given when the UMA is outputted to inform 19 the circuit 11 of extension of access time of the DRAM, and access period of the UA, LA is extended. Thus, by access of page mode system and static column system, DRAM can be accessed at high speed.