PURPOSE: To effectively utilize many processors by making each processor capable of accessing simultaneously all the parts of the memory in respect of a very large number of the processors to share one very large-scale memory by using plural path designating elements arranged in three stages.
CONSTITUTION: Many wide-word processors 11 are adopted, and they are synchronized by a common clock. A network 15 for connecting each processor 11 selectively to each memory location 13 includes plural path designating elements SA, SB, SC to be arranged in three stages, at least. The path designating elements SA, SB, SC are connected by a message to request a dissection to an address group. The path designating elements SA, SB, SC and concentrating elements CA, CB are constituted of a matrix crossbar switch. Thus, the multiplex processor 11 becomes capable of communicating with the shared memory 13, and it can be kept to be of the number of connection in which read between the elements and the number of the connected elements can be managed.
UIRIAMU AARU KURAUZAA
RANDORU DEII RETOBEEKU
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