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Patent Searching and Data


Title:
MEMORY ACCESS SYSTEM FOR DISPLAY
Document Type and Number:
Japanese Patent JPH03179491
Kind Code:
A
Abstract:

PURPOSE: To reduce the current consumption by assigning an access cycle of a KANJI(Chinese character) code for a memory when attribute data does not indicate a display of KANJI, and setting one access cycle of the KANJI code for every N cycles and assigning the remaining cycles as read/write cycles of a processor when the attribute data indicates the display of KANJI.

CONSTITUTION: When the attribute data does not indicates the display of KANJI, in a display control circuit 2, the access cycle of the KANJI code for the memory 7 is assigned as the read/write cycle of the memory 7 according to the indication of an assignment means 5. When the display of KANJI is indicated, on the other hand, one access cycle of the KANJI code for the memory 7 is set for every N cycles, the currently read KANJI code is held in a holding means 4, and the KANJI code held by the holding means 4 is used in the remaining (N-1) cycles to read a KANJI pattern out of a character pattern generating means 3. Then the remaining (N-1) cycles of the memory 7 are assigned as read/write cycles of the memory 7 for the processor 1. Consequently, the current consumption is reducible.


Inventors:
KAWASHIMA SHINICHI
Application Number:
JP31928389A
Publication Date:
August 05, 1991
Filing Date:
December 08, 1989
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G09G5/00; G09G5/22; G09G5/30; (IPC1-7): G09G5/00; G09G5/22
Attorney, Agent or Firm:
Sadaichi Igita