PURPOSE: To test an access bus of a processing device without another processing device by providing a test mode FF and its feedback circuit in a command decoding part when the system provided with two or more data processing devices and a storage device is tested.

CONSTITUTION: In case that an instruction is taken out from a storage device 2 when a test mode FF42 is set, the logical value of a signal on an output terminal 48 of a NAND circuit 43 becomes "1", and that on an output terminal 45 of a destination decoder 41 is "1", and therefore, a priority circuit part 22 is accessed. When data read/write is indicated to the storage device, the logical value of the signal on the output terminal 48 becomes "0". Then, the access to an active port 24 is performed independently of the logical value of the signal on the output signal line 45 of the destination decoder 41, and as the result, the storage device is accessed from a passive port 25 through a bus 3.