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Title:
MEMORY ADDRESSING SYSTEM
Document Type and Number:
Japanese Patent JPS584464
Kind Code:
A
Abstract:

PURPOSE: To perform a large addressing and a discontinuous addressing, by providing a memory addressing device on the way of an interface line for a data processor and a memory processor and performing a high speed address conversion.

CONSTITUTION: A conversion memory 11 for memory addressing device consists of a prefix and a plurality of address conversion tables. An entry register 14 entries address information transmitted from a data processor, the address information is entried to an entry register 14 with split to upper and lower-order addresses. An entry register 16 stores the upper-order address converted with address conversion tables 1Wn and the lower-order instruction of the address information from the data processor altogether. An entry register 18 stores a converted memory device number with the address conversion table.


Inventors:
YOKOYAMA MAKOTO
Application Number:
JP10263981A
Publication Date:
January 11, 1983
Filing Date:
June 30, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F12/02; G06F12/06; (IPC1-7): G06F13/00; G11C9/06
Attorney, Agent or Firm:
Kyotani Shiro



 
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