Title:
MEMORY BANDWIDTH CONTROL IN CORE
Document Type and Number:
Japanese Patent JP2022151658
Kind Code:
A
Abstract:
To provide a device and a system, for controlling a bandwidth in a core.SOLUTION: In a system, a core includes a local memory bandwidth monitor for each thread. The local bandwidth monitor of each thread at least allocates a bandwidth, for a memory request originating from the thread according to a class of service level stored in a field of quality of service (QoS) model-specific register (MSR). The class of service level includes the memory bandwidth monitor specified by a class of service field in a platform quality of service MSR, and execution resources to support execution of at least one thread of the core.SELECTED DRAWING: Figure 1
Inventors:
VEDVYAS SHANBHOGUE
KRISHNAKUMAR GANAPATHY
VENKATESWARA MADDURI
JAMES ALLEN
JAMES COLEMAN
STEPHEN ROBINSON
KRISHNAKUMAR GANAPATHY
VENKATESWARA MADDURI
JAMES ALLEN
JAMES COLEMAN
STEPHEN ROBINSON
Application Number:
JP2022027270A
Publication Date:
October 07, 2022
Filing Date:
February 24, 2022
Export Citation:
Assignee:
INTEL CORP
International Classes:
G06F9/50; G06F9/34
Attorney, Agent or Firm:
Patent Attorney Corporation RYUKA International Patent Office