Title:
メモリバスチェック手順
Document Type and Number:
Japanese Patent JP4291368
Kind Code:
B2
Abstract:
A method for checking usable width of a data bus linking a host device and a memory card. Preferably, at the boot up process the host device sends a test bit pattern to the memory card through the data bus. The test bit pattern can be (1010 . . . ) or (0101 . . . ). Upon receiving the test bit pattern, the memory card sends a response bit pattern to the host device through the same data bus. The response bit pattern is complement to the test bit pattern so as to allow the host device to compare the response bit pattern with the test bit pattern, and determines the usable width of the data bus based on the comparison result.
Inventors:
Fromman, Matty
Clint, Yani
Clint, Yani
Application Number:
JP2006516501A
Publication Date:
July 08, 2009
Filing Date:
May 19, 2004
Export Citation:
Assignee:
NOKIA CORPORATION
International Classes:
G06F11/22; G01R31/28; G06K17/00; G11C29/02; H04L1/24
Domestic Patent References:
| JP4279370A | ||||
| JP9321761A | ||||
| JP5227259A | ||||
| JP2000174894A | ||||
| JP2003091703A |
Foreign References:
| WO2002015020A1 |
Attorney, Agent or Firm:
Atsushi Aoki
Jun Tsuruta
Tetsuro Shimada
Shinji Takahashi
Shimichi Akihisa
Masaya Nishiyama
Jun Tsuruta
Tetsuro Shimada
Shinji Takahashi
Shimichi Akihisa
Masaya Nishiyama