Title:
MEMORY CELL ARRAY COMPRISING FERROELECTRIC CAPACITOR, MANUFACTURING METHOD THEREOF, AND FERROELECTRICS MEMORY DEVICE
Document Type and Number:
Japanese Patent JP3901432
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a memory cell array where a ferroelectrics layer constituting a ferroelectrics capacitor has a specific pattern for less floating capacity of a signal electrode, manufacturing method thereof, and a ferroelectrics memory device.
SOLUTION: In a memory cell array 100A, a memory cell comprising a ferroelectrics capacitor 20 is arrayed in matrix. The ferroelectrics capacitor 20 comprises a first signal electrode 12, a second signal electrode 16 arrayed in the direction across the first signal electrode 12, and a ferroelectrics layer 14 provided in a line along the first signal electrode 12 or the second signal electrode 16. The ferroelectrics layer 14 may be provided, in block, only in an intersection region between the first signal electrode 12 and the second signal electrode 16.
Inventors:
Eiji Natori
Kazumasa Hasegawa
Koichi Oguchi
Nao Nishikawa
Tatsuya Shimoda
Kazumasa Hasegawa
Koichi Oguchi
Nao Nishikawa
Tatsuya Shimoda
Application Number:
JP2000251436A
Publication Date:
April 04, 2007
Filing Date:
August 22, 2000
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
H01L21/8246; H01L27/105; G11C11/22; H01L21/02; H01L27/10; (IPC1-7): H01L27/105
Domestic Patent References:
| JP8255879A | ||||
| JP9249972A | ||||
| JP10303378A |
Attorney, Agent or Firm:
Yukio Fuse
Mitsue Obuchi
Mitsue Obuchi