Title:
MEMORY CELL ARRAY AND SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPH05314776
Kind Code:
A
Abstract:
PURPOSE: To reduce the occupancy area of a RAM and a ROM related to a semiconductor memory, related to a memory array and the semiconductor memory integrating the ROM and the RAM on the same chip in detail.
CONSTITUTION: In the memory cell array 2 connecting the RAM cells 1 respectively between plural word lines ML and plural bit lines BL, BL', the RAM cells group 1 of a part of the memory cell array 2 is formed to the memory cells 3 group whose storage values are an unrewritable fixed storage value.
Inventors:
KIKUTA KAZUYOSHI
Application Number:
JP11917392A
Publication Date:
November 26, 1993
Filing Date:
May 12, 1992
Export Citation:
Assignee:
FUJITSU LTD
FUJITSU VLSI LTD
FUJITSU VLSI LTD
International Classes:
G11C11/41; G11C11/401; G11C14/00; G11C17/00; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): G11C11/41; G11C11/401; G11C17/00; H01L27/10
Attorney, Agent or Firm:
Hironobu Onda