PURPOSE: To match writing timing and reading timing between respective RAMs by employing a common layout of writing and reading circuits in single port RAM end multi-port RAM.

CONSTITUTION: In a memory cell circuit having a plurality of reading ports and writing ports, an identical circuit layout is employed in each port. Identical positional relationship and circuit are employed in the layout of writing and reading bit line pairs 7, 8 and 18, 19 for first port and the writing and reading bit line pairs 23, 24 and 32, 33 for second port.