Title:
メモリセル情報の読み出し回路および半導体記憶装置
Document Type and Number:
Japanese Patent JP4052895
Kind Code:
B2
Abstract:
A reading circuit for reading information stored in a memory cell includes a current supply circuit for supplying a current to a bit line connected to the memory cell; a comparison circuit for comparing a potential of the bit line supplied with the current by the current supply circuit with a reference potential so as to output the information stored in the memory cell; a disconnection circuit for electrically disconnecting the comparison circuit and the memory cell from each other under a prescribed condition; a charge circuit for charging the bit line, the charge circuit stopping charging of the bit line when the potential of the bit line exceeds a prescribed potential; and a discharge circuit for discharging the bit line when the potential of the bit line exceeds the prescribed potential.
Inventors:
Yoshinao Morikawa
Application Number:
JP2002229722A
Publication Date:
February 27, 2008
Filing Date:
August 07, 2002
Export Citation:
Assignee:
Sharp Corporation
International Classes:
G11C16/06; G11C7/06; G11C11/15; G11C11/16; G11C16/00; G11C16/28
Domestic Patent References:
| JP2000311493A | ||||
| JP2000048585A | ||||
| JP2301100A | ||||
| JP2001184881A | ||||
| JP2002197853A |
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Takeshi Oshio
Takaaki Yasumura
Takeshi Oshio