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Title:
MEMORY CIRCUIT
Document Type and Number:
Japanese Patent JPS61255600
Kind Code:
A
Abstract:

PURPOSE: To delay an optional signal without disturbing a wave form of an internal signal and unsealing a case by controlling a driving of an addressbuffer, a delay program circuit by address signals of different thresholds.

CONSTITUTION: When an address input terminal Ai is brought to above a first threshold, an address buffer 10 is driven. When this terminal Ai is brought to above a second threshold voltage higher than the first threshold voltage, an N channel transistor Q2 of a delay program circuit is turned on through an N channel transistor Q1, and a fuse 6 is melted. Thereby, an output of a circuit passing through an inverter 1 is reversed to H and a capacitor C of a delay circuit 12 is connected and by a change of a time constant, a signal of a desired delay section N is delayed. Thus, an optional signal of a memory circuit is easily and accurately delayed without disturbing an internal signal and unsealing.


Inventors:
SANADA KOJI
Application Number:
JP9710885A
Publication Date:
November 13, 1986
Filing Date:
May 08, 1985
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F11/22; G11C29/00; G11C29/50; (IPC1-7): G06F11/22; G11C29/00
Attorney, Agent or Firm:
Uchihara Shin



 
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