Title:
メモリ回路、集積回路装置及び電子機器
Document Type and Number:
Japanese Patent JP5382381
Kind Code:
B2
Abstract:
The disclosed device has memory cells provided with transistors and variable resistance elements, and contains memory blocks (10) consisting of N number of memory cells sequentially connected in series. One end of a first transistor (T1) is connected to a bit line (BL1). The variable resistance elements (RC1-RC4) contain a plurality of carbon nanotubes disposed between two electrodes, can have either a low resistance state wherein the resistance element has a relatively low resistance, or a high resistance state wherein the resistance element has a relatively high resistance, and sustain either the high resistance state or the low resistance state when voltage and current are not applied between the two electrodes.
Inventors:
Katsuhiko Hieda
Osamu Aoki
Osamu Aoki
Application Number:
JP2011538297A
Publication Date:
January 08, 2014
Filing Date:
September 01, 2010
Export Citation:
Assignee:
JSR CORPORATION
International Classes:
G11C13/00; G11C11/50; H01L27/10; H01L27/105
Domestic Patent References:
| JP2008541458A | 2008-11-20 | |||
| JP2008198948A | 2008-08-28 | |||
| JP2008269741A | 2008-11-06 | |||
| JP2007049084A | 2007-02-22 | |||
| JP2008541458A | 2008-11-20 | |||
| JP2008198948A | 2008-08-28 |
Attorney, Agent or Firm:
Mitsue Obuchi
Yukio Fuse
Mitsufumi Matsumoto
Yukio Fuse
Mitsufumi Matsumoto