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Patent Searching and Data


Title:
MEMORY CONTROL APPARATUS
Document Type and Number:
Japanese Patent JP2003131940
Kind Code:
A
Abstract:

To provide a memory control apparatus that can solve a problem of increase in a number of memory controller terminals when a plurality type of flash memory devices with different interface specifications are attached to the controller, and the problem of the necessity to convert a controller action mode into a static state or an inability to connect the plurality type of the memory devices, at the same time, to the controller when a signal line is simply multiplexed to avoid the increase in the number of the memory controller terminals.

Connecting terminals for a memory control apparatus are divided into a common connecting signal terminal and an individual connecting signal terminal, a signal for selecting a memory device is assigned to the terminals as an individual connecting signal, and the common connecting signal terminal is shared among memory devices.


Inventors:
TERADA KOICHI
NOJIRI TORU
NISHIOKA KIYOKAZU
EHAMA MASAKAZU
Application Number:
JP2001327110A
Publication Date:
May 09, 2003
Filing Date:
October 25, 2001
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F12/06; G06F12/00; G06F13/16; (IPC1-7): G06F12/06; G06F12/00
Attorney, Agent or Firm:
Sakuta Yasuo