MEMORY CONTROL CIRCUIT AND CACHE MEMORY

Title:

MEMORY CONTROL CIRCUIT AND CACHE MEMORY

Document Type and Number:

Japanese Patent JP2015052938

Kind Code:

A

Abstract:

PROBLEM TO BE SOLVED: To prevent a fault which disables normal memory access due to an error of a cache memory.SOLUTION: A memory control circuit includes: an error detection unit which detects whether or not an error is included in data written to a cache memory or data read from the cache memory; an error correction unit which corrects the error detected by the error detection unit; an error determination unit which, if it is detected by the error detection unit that an error is included in data read out in order to verify data written by data write to the cache memory or in data read out by data readout from the cache memory, determines whether the number of error bits is larger than a prescribed threshold set on the basis of the maximum number of error bits which the error correction unit can correct; and an access control unit which controls whether or not to access a memory lower than the cache memory and whether or not to perform error correction by the error correction unit, on the basis of the determination result of the error determination unit.

Inventors:

NOGUCHI HIROKI
FUJITA SHINOBU
ABE KEIKO

Application Number:

JP2013185676A

Publication Date:

March 19, 2015

Filing Date:

September 06, 2013

Export Citation:

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