Title:
メモリ制御回路とメモリシステム、及びそのメモリ制御方法、及び集積回路
Document Type and Number:
Japanese Patent JP5019573
Kind Code:
B2
Abstract:
Provided is a memory control apparatus for controlling a plurality of memories (203 - 206), each of which includes a respective terminating circuit (701) for preventing signal reflection in the corresponding memory. The memory control apparatus comprises:
a memory command controller (102) configured to assert an On-Die Termination (ODT) enable signal (110);
a memory data controller (101) configured to control a data transmission between a bus interface (103) and at least one of the plurality of memories based on a timing signal (115) output by the memory command controller; and
an ODT controller(112) configured to assert ODT signals (302) to the plurality of memories via a delay circuit (116) based on the ODT enable signal (110) asserted by the memory command controller (102),
wherein the memory command controller (102) asserts the ODT enable signal (110) in advance to adjust a delay of the delay circuit.
Inventors:
Murayama
Takeshi Suzuki
Takeshi Suzuki
Application Number:
JP2006284142A
Publication Date:
September 05, 2012
Filing Date:
October 18, 2006
Export Citation:
Assignee:
Canon Inc
International Classes:
G06F12/00; G06F13/16; G11C11/401; G11C11/407
Domestic Patent References:
| JP2003068082A | ||||
| JP2006516059A | ||||
| JP2005285125A | ||||
| JP2003197753A | ||||
| JP2007233589A | ||||
| JP2007241799A | ||||
| JP2002268941A | ||||
| JP2003345735A |
Attorney, Agent or Firm:
Yasunori Otsuka
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura