To provide a memory control circuit for preventing malfunction due to the delay of access even at the time of continuously performing access to a plurality of different banks.
This memory control circuit is provided with a control circuit which controls access to a memory having a plurality of banks. This memory control circuit is provided with an access deciding circuit which decides an access method to the memory based on the first signal for selectively designating the addresses of the plurality of banks and a second signal for selectively activating the plurality of banks. The access deciding circuit is configured to control the control circuit in order to set a period to inactivate the plurality of banks when the activation of the plurality of banks is switched based on the decision result when the first signal shows the designation of the plurality of banks, and the second signal shows the continous activation of the plurality of banks.
KATO HIDEKAZU
FURUKAWA RIICHI
ARAI YOSHIMASA
Next Patent: IMAGE COMPOSING DEVICE AND IMAGE COMPOSING METHOD