PURPOSE: To prevent the occurrence of a parity error at the time of adding a parity bit and to surely write high reliability data in a memory control circuit.

CONSTITUTION: By an oscillation detection part 2, the data from a memory part 1 are monitored, and an interruption reprocess request signal is outputted to a memory control part 3 when the data are changed while a check timing signal from the memory control part 3 is inputted. By the memory control part 3, invalidates the parity error processing of the data in a system and performs the rewrite request in the memory part 1 when the interruption reprocess request signal is inputted from the oscillation detection part 2.