Title:
メモリ制御装置、メモリ制御プログラムおよびメモリ制御方法
Document Type and Number:
Japanese Patent JP7132491
Kind Code:
B2
Abstract:
A memory control apparatus includes a first memory, a second memory, a third memory, and a processor configured to add, to management information, first identification information and information indicating a position where first data is stored when the first data is stored in the first memory, add, to the management information, the first identification information and information indicating a position where second data is stored when the second data is stored in the second memory, add, to the management information, second identification information and information indicating a position where third data is stored when the third data is stored in the third memory, determine which one of the first identification information and the second identification information is associated with fourth data, and perform retrieval of the fourth data from the first memory or the second memory in accordance with information indicating a position where the fourth data is stored.
Inventors:
Kazama Satoshi
Shinya Kuwamura
Shinya Kuwamura
Application Number:
JP2018093154A
Publication Date:
September 07, 2022
Filing Date:
May 14, 2018
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F12/0888; G06F12/0811; G06F12/1009
Domestic Patent References:
| JP2017058951A | ||||
| JP2017138823A | ||||
| JP2017138853A |
Foreign References:
| WO2011033600A1 | ||||
| US20080270758 | ||||
| US20140013045 |
Attorney, Agent or Firm:
Fuso International Patent Office
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