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Title:
MEMORY CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS60101658
Kind Code:
A
Abstract:

PURPOSE: To attain a dynamic change of each area range by dividing the inside of the same memory into optional areas to use the areas as an area for action of an error detection parity or an area for an error correcting.

CONSTITUTION: Memory parts 402 and 404 having at least a 1-bit parity area added are provided to memory parts 401W404. An error correction flag register FF413 gives an indication to the parts 401W404 in an error correction system for writing of data. An error correction write control part 405 controls the data writing to the parts 401W404 by an output 456 of the FF413 in a parity check system or an error correction system. An error correction read part 406 decides the parity check system or the error correction system for output data on parity areas 402 and 404 and controls a parity checker 104, a code checker 304 and a 1-bit error correction part 12. Thus it is possible to write data to an optional area of the memory part in the parity check system or the error correction system.


Inventors:
IKUMA JIYUNICHI
Application Number:
JP1983000209450
Publication Date:
June 05, 1985
Filing Date:
November 08, 1983
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F11/10; G06F12/16; (IPC1-7): G06F11/10