Title:
MEMORY CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS63240662
Kind Code:
A
Abstract:
PURPOSE:To enable plural decentralized processing parts to work independently of a main processing part and to improve the performance of a memory control system, by providing a single machine cycle between access cycles when the continuous accesses are given to the decentralized memory parts from the decentralized processing parts and accepting the access request in said idle cycle from the main processing part. CONSTITUTION:A single access cycle is defined as a 3-machine cycle and an idle 1-machine cycle is provided only when the access requests are given continuously from the decentralized processing parts 3. Then the acceptance of the next request is delayed by a single machine cycle under the control of the decentralized memory control parts 4. Thus the accesses given to the decentralized memory parts 5 from a main processing part 1 can be accepted in said idle cycle. Furthermore an access is possible synchronously with the action of the remote side. Thus the parts 3 can work independently of the requests of the part 1 and the performance of a memory control system is improved.
Inventors:
YONEZAWA MASASHI
YOSHIZAKI KATSUHIRO
YOSHIZAKI KATSUHIRO
Application Number:
JP7298687A
Publication Date:
October 06, 1988
Filing Date:
March 28, 1987
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G06F15/16; G06F13/16; G06F15/177; (IPC1-7): G06F15/16
Domestic Patent References:
| JPS60113393A | 1985-06-19 | |||
| JP61193599B | ||||
| JPS61240359A | 1986-10-25 |
Attorney, Agent or Firm:
Kenjiro Take