Title:
MEMORY CONTROLLER AND DATA PROCESSOR
Document Type and Number:
Japanese Patent JP2010134628
Kind Code:
A
Abstract:
To provide a memory controller and a data processor for grouping requests from a plurality of memory access requesters in order to increase the use efficiency of a bus.
A request queue 22 stores requests received from a plurality of memory access requesters. A merge section 31 merges requests accessible in one read cycle or write cycle in a DDR2-SDRAM among requests in the request queue 22. A memory interface part 27 accesses the DDR2-SDRAM according to the requests, and accesses the DDR2-SDRAM in response to the merged requests in a batch.
COPYRIGHT: (C)2010,JPO&INPIT
Inventors:
KOYAMA MASAYUKI
Application Number:
JP2008308795A
Publication Date:
June 17, 2010
Filing Date:
December 03, 2008
Export Citation:
Assignee:
RENESAS TECH CORP
International Classes:
G06F12/00; G06F12/02
Domestic Patent References:
| JP2007249837A | 2007-09-27 | |||
| JPH0581042A | 1993-04-02 | |||
| JPH06195313A | 1994-07-15 | |||
| JPH07253923A | 1995-10-03 | |||
| JP2002328837A | 2002-11-15 | |||
| JP2006260472A | 2006-09-28 | |||
| JP2005339348A | 2005-12-08 | |||
| JPH06162066A | 1994-06-10 | |||
| JPH0496841A | 1992-03-30 |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa